Programmable shift registers have conventionally been used to provide variable (e.g., adjustable) delays of blocks of data in video and other systems, for purposes such as frame synchronization, ghost cancellation, etc. FIG. 1 provides a block diagram of a typical prior art variable shift register of a conventional form. In operation of the FIG. 1 shift register, delay of a block of input data is achieved basically by reading the data into and out of one or more of a series of registers R1 -Ri, as selected via a delay decoder, on a timed basis as controlled by a clock signal. If reading into and out of a single register produces one increment of delay, a desired delay of ten delay increments is achieved by successively reading the data into and out of ten registers. An extended delay capability thus entails a large number of registers and complex support circuitry, with accompanying attributes of relatively high power consumption and extensive semiconductor size requirements resulting in increased manufacturing and operating costs. A conventional shift register, such as illustrated in FIG. 1, is described in greater detail in U.S. Pat. No. 4,953,128, issued Aug. 28, 1990.
In the prior art, efforts have been made to address the cost and operating disadvantages of conventional shift registers by replacing a shift register with a RAM circuit configured to provide a variable delay. Thus, where a video line or frame, for example, is to be delayed by being subjected to a repetitive read/write cycle of total duration corresponding to a desired delay, arrangements have been described whereby the desired result is provided by use of a single RAM array. The RAM thus replaces the series of individual registers as shown in FIG. 1, in order to provide a variable delay for a single block of input data. Single port RAM delay arrangements are shown and the basics of operation are described in some detail, in U.S. Pat. Nos. 4,953,128 (noted above) and 4,876,670, issued Oct. 24, 1989.
However, in a ghost cancellation system or digital communications equalizer, a large number of individual variable delays are required. Typically, each tap bank in the system architecture will entail a requirement for a separate variable delay facility which is individually adjustable to provide a selectable delay. Thus, even with a bank of registers in a shift register replaced by a single RAM array, a very large number of RAM arrays will still be required in such applications.
Certain characteristics of variable delay requirements in a typical application have now been recognized as background for the present invention. In such an application, considered by way of example:
(a) the maximum required delay is equal to 512 delay increments;
(b) the summation of various related variable delay values does not exceed 512 delay increments; and
(c) the value of such various delays does not follow any predictable pattern (i.e., the various delay values can individually be as big as 512 delay increments, or as small as very few delay increments).
According to the conventional approach, each tap bank would require its own dedicated shift register or RAM array capable of providing 512 increments of delay, in order to implement a variable delay circuit for each individual tap bank. Thus, even with the basic advantages of RAM circuit arrangements, there remain significant manufacturing and operational costs which cannot be avoided.
It is therefore an object of this invention to provide economical variable delay circuits having a multiple-delay capability whereby a plurality of blocks of input data may simultaneously be subjected to different delays by use of only a single RAM array.
It is an additional object to provide a variable delay circuit utilizing a RAM array having a given number of storage locations, such as 512, to delay a plurality of blocks of input data by different delays which aggregate not more than 512 delay increments.
Further objects are to provide new and improved variable delay circuits having a multiple-delay capability whereby one or more blocks of input data may be simultaneously delayed corresponding to the selected delay time.